module memory_controller
(
  //OUTPUTS
  output bank0_en,        //Enables writting in bank 0 - this signal is specific to memory type
  output bank1_en,        //Enables writting in bank 1 - this signal is specific to memory type
  output mem_rdy,         //Indicates that operation in memory is ready - this is standard interface
  //INPUTS
  input mem_rd,           //Read memory signal    - this is standard interface
  input mem_wr,           //Write memory signal   - this is standard interface
  input [1:0] bank_sel    //Select bank of memory - this is standard interface
);

//This implementation is specific to memory bank composed of Flip Flops
//However, the signals below are standardized: 
//                      - mem_rd
//                      - mem_wr
//                      - mem_rdy
//                      - bank_sel
// The signals provides the communication between the memory controller and the FFT core

wire BANK_ALL;
//=============================================================================
// 1)  Bank Selector Table
//=============================================================================
localparam BANK_01  = 2'b00;
localparam BANK_10  = 2'b01;
localparam BANK_0   = 2'b10;
localparam BANK_1   = 2'b11;
assign     BANK_ALL = ( bank_sel == BANK_01 ||
                        bank_sel == BANK_10  );

assign bank0_en = (mem_wr && (bank_sel == BANK_0 || BANK_ALL));
assign bank1_en = (mem_wr && (bank_sel == BANK_1 || BANK_ALL));
assign mem_rdy  = 1'b1;
endmodule
